Secure Hardware Design (Paperback)

The services and security benefits provided by cryptographic algorithms are indispensable for modern electronic infrastructure. To provide benefit to a larger system, however, the algorithms themselves must be implemented securely. Devices implementing cryptographic algorithms can leak secret information to any observer through side channels limiting their security. Powerful attacks have been developed with conscientiously exploit the side information to completely compromise the security of an implementation within minutes. This thesis investigates the sources of vulnerabilities and proposed counter measures against attacks which use power consumption and behavior in the presence of faults of a device as the target for an attack. The proposed counter measures for the power and fault attacks are based on the non linear error-detecting codes known as robust codes and a synchronous gate level circuit structures.